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MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Order Number: MPC9449/D Rev 1, 08/2002
3.3V/2.5V 1:15 PECL/LVCMOS Clock Fanout Buffer
The MPC9449 is a 3.3V or 2.5V compatible, 1:15 clock fanout buffer targeted for high performance clock tree applications. With output frequencies up to 200 MHz and output skews less than 200 ps the device meets the needs of the most demanding clock applications. Features * 15 LVCMOS compatible clock outputs
MPC9449
* Two selectable LVCMOS and one differential LVPECL compatible clock
3.3V/2.5V 1:15 PECL/LVCMOS CLOCK FANOUT BUFFER
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Supports clock distribution in networking, telecommunication and FA SUFFIX computing applications 52 LEAD LQFP PACKAGE CASE 848D * Pin and function compatible to MPC949 Functional Description The MPC9449 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 200 MHz. The device has 15 identical outputs, organized in 4 output banks. Each output bank provides a retimed or frequency divided copy of the input signal with a near zero skew. The output buffer supports driving of 50 terminated transmission lines on the incident edge: each output is capable of driving either one parallel terminated or two series terminated transmission lines. Two selectable LVCMOS compatible clock inputs are available. This feature supports redundant differential clock sources. In addition, the MPC9449 accepts one differential PECL clock signal. The DSELx pins choose between division of the input reference frequency by one or two. The frequency divider can be set individually for each of the four output banks. Applying the OE control will force the outputs into high-impedance mode. All inputs have an internal pull-up or pull-down resistor preventing unused and open inputs from floating. The device supports a 2.5V or 3.3V power supply and an ambient temperature range of -40C to +85C. The MPC9449 is pin and function compatible but performance-enhanced to the MPC949. The device is packaged in a 52-lead LQFP package.
* * * * * * * * *
inputs Selectable output frequency divider (divide-by-one and divide-by-two) Maximum clock frequency of 200 MHz Maximum clock skew of 200 ps High-impedance output control 3.3V or 2.5V power supply Drives up to 30 series terminated clock lines Ambient temperature range -40C to +85C 52 lead LQFP packaging
(c) Motorola, Inc. 2002
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MPC9449
DSELA 0 QA0 QA1 QB0
VCC
1 CCLK0 CCLK1 CCLK_SEL 0 0 1 1
/1 /2
0
GND
GND
GND
VCC
VCC
QC0
QC1
QC2
QC3
QD5
NC
1 QB2 QC0 0 QC1 QC2 QC3
VCC
PCLK PCLK
NC VCC QB2 GND QB1 VCC QB0 GND GND QA1 VCC QA0 GND
39 38 37 36 35 34 33 32 31 30 29 28 27 40 26 41 42 43 44 45 46 47 48 49 50 51 52 1 2 3 4 5 6 7 8 9 10 11 12 13 25 24 23 22 21
NC
QB1
GND
NC VCC QD4 GND QD3 VCC QD2 GND QD1 VCC QD0 GND NC
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1 PCLK_SEL
DSELB DSELC
QD0 QD1 0 QD2 1 QD3
MPC9449
20 19 18 17 16 15 14
DSELD QD4 QD5
CCLK_SEL
PCLK_SEL
CCLK0
CCLK1
DSELC
DSELD
DSELA
MR/OE
DSELB
PCLK
PCLK
VCC
MR/OE
Figure 1. MPC9449 Logic Diagram Table 1: FUNCTION TABLE
Control PCLK_SEL CCLK_SEL DSELA, DSELB, DSELC, DSELD MR/OE Default 0 0 00 00 1 0
Figure 2. MPC9449 52-Lead Package Pinout (Top View)
1 PCLK differential input selected CCLK1 selected /2 Outputs disabled (high impedance)
LVCMOS clock input selected (CCLK0 or CCLK1) CCLK0 selected /1 Outputs enabled
Table 2: PIN CONFIGURATION
Pin PCLK, PCLK CCLK0, CCLK1 PCLK_SEL CCLK_SEL DSELA, DSELB, DSELC, DSELD MR/OE QA0-1, QB0-2, QC0-3, QD0-5 GND VCC I/O Input Input Input Input Input Input Output Supply Supply Type LVPECL LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS LVCMOS Ground VCC Differential LVPECL clock input LVCMOS clock inputs LVPECL clock input select LVCMOS clock input select Clock divider selection Output enable/disable (high-impedance tristate) Clock outputs Negative power supply (GND) Positive power supply for I/O and core. All VCC pins must be connected to the positive power supply for correct operation Function
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GND
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MPC9449
Table 3: GENERAL SPECIFICATIONS
Symbol VTT MM HBM LU CPD CIN Characteristics Output Termination Voltage ESD Protection (Machine Model) ESD Protection (Human Body Model) Latch-Up Immunity Power Dissipation Capacitance Input Capacitance 200 2000 200 12 4.0 Min Typ VCC
B2
Max
Unit V V V mA pF pF
Condition
Per output Inputs
Table 4: ABSOLUTE MAXIMUM RATINGSa
Symbol VCC VIN Supply Voltage DC Input Voltage DC Output Voltage DC Input Current DC Output Current Characteristics Min -0.3 -0.3 -0.3 Max 3.8 VCC+0.3 VCC+0.3 20 50 Unit V V V mA mA Condition
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VOUT IIN IOUT
TS Storage Temperature -65 125 C a. Absolute maximum continuous ratings are those maximum values beyond which damage to the device may occur. Exposure to these conditions or conditions beyond those indicated may adversely affect device reliability. Functional operation at absolute-maximum-rated conditions is not implied.
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Freescale Semiconductor, Inc.
MPC9449
Table 5: DC CHARACTERISTICS (VCC = 3.3V 5%, TA = -40C to 85C)
Symbol VIH VIL VOH VPP VCMRb VOL ZOUT IIN Characteristics Input high voltage Input low voltage Output High Voltage Peak-to-peak input voltage Common Mode Range Output Low Voltage Output impedance 14 - 17 PCLK, PCLK PCLK, PCLK 2.4 250 1.0 VCC-0.6 0.55 0.30 Min 2.0 Typ Max VCC + 0.3 0.8 Unit V V V mV V V V Condition LVCMOS LVCMOS IOH=-24 mAa LVPECL LVPECL IOL= 24 mA IOL= 12 mA
W
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Input Current 200 A VIN=VCC or GND ICCQ Maximum Quiescent Supply Current 10 mA All VCC Pins a The MPC9449 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Alternatively, the device drives up to two 50 series terminated transmission lines. b VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification.
Table 6: AC CHARACTERISTICS (VCC = 3.3V 5%, TA = -40C to 85C)a
Symbol VPP VCMRc fmax fref tP, REF tr, tf tsk(O) Characteristics Peak-to-peak input voltage Common Mode Range Output frequency Input Frequency Reference Input Pulse Width CCLK0, CCLK1 Input Rise/Fall Time Output-to-output Skew Qa outputs Qb outputs Qc outputs Qd outputs All outputs All outputs 2.5 250 CCLK0 or CCLK1 to any Q PCLK to any Q OE to any Q OE to any Q 0.1 1.0 1.0 3.0 3.0 5.0 5.0 11 11 1.0 PCLK, PCLK PCLK, PCLK Min 400 1.0 0 0 1.5 1.0 50 50 50 100 200 300 Typ Max 1000 VCC-0.6 200 200 Unit mV V MHz MHz ns ns ps ps ps ps ps ps ns ps ns ns ns ns ns 0.55 to 2.4V DCREF = 50% 0.8 to 2.0V Condition LVPECL LVPECL
same frequency different frequencies tsk(PP) tsk(P) tPLH, HL tPLZ, HZ tPZL, LZ tr, tf Device-to-device Skew Output Pulse Skew Propagation delay Output Disable Time Output Enable Time Output Rise/Fall Timec
tJIT(CC) Cycle-to-cycle jitter RMS (1 ) TBD ps a AC characteristics apply for parallel output termination of 50 to VTT. b VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts propagation delay. c An input rise/fall time greater than that specified may be used, but AC characteristics are not guaranteed under such a condition.
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MPC9449
Table 7: DC CHARACTERISTICS (VCC = 2.5V 5%, TA = -40C to 85C)
Symbol VIH VIL VPP VCMRa VOH VOL ZOUT IIN a Characteristics Input high voltage Input low voltage Peak-to-peak input voltage Common Mode Range Output High Voltage Output Low Voltage Output impedance Input Currentc 17 - 20 200 PCLK, PCLK PCLK, PCLK Min 1.7 -0.3 250 1.0 1.8 0.6 VCC-0.6 Typ Max VCC + 0.3 0.7 Unit V V mV V V V Condition LVCMOS LVCMOS LVPECL LVPECL IOH=-15 mAb IOL= 15 mA
W
A
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b c
VIN=VCC or GND ICC Maximum Quiescent Supply Current 10 mA All VCC Pins VCMR (DC) is the crosspoint of the differential input signal. Functional operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (DC) specification. The MPC9449 is capable of driving 50 transmission lines on the incident edge. Each output drives one 50 parallel terminated transmission line to a termination voltage of VTT. Inputs have pull-down or pull-up resistors affecting the input current.
Table 8: AC CHARACTERISTICS (VCC = 2.5V 5%, TA = -40C to 85C)a
Symbol VPP VCMRb fmax fref tP, REF tr, tf tsk(O) Characteristics Peak-to-peak input voltage Common Mode Range Output frequency Input Frequency Reference Input Pulse Width CCLK Input Rise/Fall Time Output-to-output Skew Qa outputs Qb outputs Qc outputs Qd outputs All outputs All outputs 5.0 350 CCLK0 or CCLK1 to any Q PCLK to any Q OE to any Q OE to any Q 0.1 1.0 1.0 3.5 3.5 7.0 7.0 11 11 1.0 PCLK, PCLK PCLK, PCLK Min 400 1.2 0 0 1.5 1.0 50 50 50 100 200 300 Typ Max 1000 VCC-0.6 200 200 Unit mV V MHz MHz ns ns ps ps ps ps ps ps ns ps ns ns ns ns ns 0.6 to 1.8V DCREF = 50% 0.7 to 1.7V Condition LVPECL LVPECL
same frequency different frequencies tsk(PP) tSK(P) tPLH, HL tPLZ, HZ tPZL, LZ tr, tf Device-to-device Skew Output Pulse Skew Propagation delay Output Disable Time Output Enable Time Output Rise/Fall Timec
tJIT(CC) Cycle-to-cycle jitter RMS (1 ) TBD ps a AC characteristics apply for parallel output termination of 50 to VTT. b VCMR (AC) is the crosspoint of the differential input signal. Normal AC operation is obtained when the crosspoint is within the VCMR range and the input swing lies within the VPP (AC) specification. Violation of VCMR or VPP impacts propagation delay. c An input rise/fall time greater than that specified may be used, but AC characteristics are not guaranteed under such a condition.
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Freescale Semiconductor, Inc.
MPC9449
APPLICATIONS INFORMATION
Driving Transmission Lines The MPC9449 clock driver was designed to drive high speed signals in a terminated transmission line environment. To provide the optimum flexibility to the user the output drivers were designed to exhibit the lowest impedance possible. With an output impedance of less than 20 the drivers can drive either parallel or series terminated transmission lines. For more information on transmission lines the reader is referred to Motorola application note AN1091. In most high performance clock networks point-to-point distribution of signals is the method of choice. In a point-to-point scheme either series terminated or parallel terminated transmission lines can be used. The parallel technique terminates the signal at the end of the line with a 50 resistance to VCC/2. This technique draws a fairly high level of DC current and thus only a single terminated line can be driven by each output of the MPC9449 clock driver. For the series terminated case however there is no DC current draw, thus the outputs can drive multiple series terminated lines. Figure 3. "Single versus Dual Transmission Lines" illustrates an output driving a single series terminated line versus two series terminated lines in parallel. When taken to its extreme the fanout of the MPC9449 clock driver is effectively doubled due to its capability to drive multiple lines.
MPC9449 OUTPUT BUFFER IN
14
impedance does not match the parallel combination of the line impedances. The voltage wave launched down the two lines will equal: = VS ( Z0 / (RS+R0 +Z0)) = 50 || 50 = 36 || 36 = 14 = 3.0 ( 25 / (18+17+25) = 1.31V At the load end the voltage will double, due to the near unity reflection coefficient, to 2.6V. It will then increment towards the quiescent 3.0V in steps separated by one round trip delay (in this case 4.0ns). VL Z0 RS R0 VL 1. Final skew data pending specification.
3.0 OutA tD = 3.8956 OutB tD = 3.9386
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2.5
VOLTAGE (V)
2.0 In 1.5
1.0
0.5 RS = 36 ZO = 50 OutA 0 2 4 6 8 TIME (nS) 10 12 14
MPC9449 OUTPUT BUFFER IN
14
Figure 4. Single versus Dual Waveforms
RS = 36 ZO = 50 OutB0
RS = 36
ZO = 50 OutB1
Figure 3. Single versus Dual Transmission Lines The waveform plots in Figure 4. "Single versus Dual Line Termination Waveforms" show the simulation results of an output driving a single line versus two lines. In both cases the drive capability of the MPC9449 output buffer is more than sufficient to drive 50 transmission lines on the incident edge. Note from the delay measurements in the simulations a delta of only 43ps exists between the two differently loaded outputs. This suggests that the dual line driving need not be used exclusively to maintain the tight output-to-output skew of the MPC9449. The output waveform in Figure 4. "Single versus Dual Line Termination Waveforms" shows a step in the waveform, this step is caused by the impedance mismatch seen looking into the driver. The parallel combination of the 36 series resistor plus the output
Since this step is well above the threshold region it will not cause any false clock triggering, however designers may be uncomfortable with unwanted reflections on the line. To better match the impedances when driving multiple lines the situation in Figure 5. "Optimized Dual Line Termination" should be used. In this case the series terminating resistors are reduced such that when the parallel combination is added to the output buffer impedance the line impedance is perfectly matched.
MPC9449 OUTPUT BUFFER
14
RS = 22
ZO = 50
RS = 22
ZO = 50
14 + 22 k 22 = 50 k 50 25 = 25 Figure 5. Optimized Dual Line Termination
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MPC9449
MPC9449 DUT Pulse Generator Z = 50W ZO = 50 ZO = 50
RT = 50 VTT
RT = 50 VTT
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Figure 6. CCLK MPC9449 AC test reference for Vcc = 3.3V and Vcc = 2.5V
Differential Pulse Generator Z = 50
ZO = 50
MPC9449 DUT ZO = 50
W
RT = 50 VTT
RT = 50 VTT
Figure 7. PCLK MPC9449 AC test reference
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MPC9449
VCC VCC VCC VCC
B2 B2
CCLK
VCC VCC VCC VCC
B2 B2
GND
GND QX
GND tSK(O) The pin-to-pin skew is defined as the worst case difference in propagation delay between any similar delay path within a single device t(LH) t(HL)
GND
Figure 8. Output-to-output Skew tSK(O)
Figure 9. Propagation delay (tPD) test reference
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PCLK PCLK VPP VCMR VCC VCC t(LH) t(HL)
CCLK
VCC VCC VCC VCC
B2 B2
GND
QX
B2
QX
GND t(LH) t(HL) tSK(P) = | tPLH - tPHL |
GND
Figure 10. Propagation delay (tPD) test reference
Figure 11. Output Pulse Skew tSK(P) test reference
VCC=3.3V 2.4 0.55 tF tR
VCC=2.5V 1.8V 0.6V TN TN+1 TJIT(CC) = |TN -TN+1 |
The variation in cycle time of a signal between adjacent cycles, over a random sample of adjacent cycle pairs
Figure 12. Output Transition Time Test Reference
Figure 13. Cycle-to-cycle Jitter
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MPC9449
OUTLINE DIMENSIONS
FA SUFFIX LQFP PACKAGE CASE 848D-03 ISSUE C
4X 4X TIPS
0.20 (0.008) H L-M N
0.20 (0.008) T L-M N C L
-X- X=L, M, N
52 1
40 39
AB AB
G
3X VIEW
Y -M- B V
PLATING
-L-
VIEW Y F
BASE METAL
Freescale Semiconductor, Inc...
B1
13 14 26 27
V1
J
0.13 (0.005)
A1 S1 A S
-N-
SECTION AB-AB
ROTATED 90_ CLOCKWISE NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -H- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -L-, -M- AND -N- TO BE DETERMINED AT DATUM PLANE -H-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -T-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.25 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -H-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE LEAD WIDTH TO EXCEED 0.46 (0.018). MINIMUM SPACE BETWEEN PROTRUSION AND ADJACENT LEAD OR PROTRUSION 0.07 (0.003). MILLIMETERS MIN MAX 10.00 BSC 5.00 BSC 10.00 BSC 5.00 BSC --- 1.70 0.05 0.20 1.30 1.50 0.20 0.40 0.45 0.75 0.22 0.35 0.65 BSC 0.07 0.20 0.50 REF 0.08 0.20 12.00 BSC 6.00 BSC 0.09 0.16 12.00 BSC 6.00 BSC 0.20 REF 1.00 REF 0_ 7_ --- 0_ 12 _ REF 5_ 13 _ INCHES MIN MAX 0.394 BSC 0.197 BSC 0.394 BSC 0.197 BSC --- 0.067 0.002 0.008 0.051 0.059 0.008 0.016 0.018 0.030 0.009 0.014 0.026 BSC 0.003 0.008 0.020 REF 0.003 0.008 0.472 BSC 0.236 BSC 0.004 0.006 0.472 BSC 0.236 BSC 0.008 REF 0.039 REF 0_ 7_ --- 0_ 12 _ REF 5_ 13 _
C -H- -T-
SEATING PLANE
4X
2 0.10 (0.004) T
4X
3 VIEW AA
0.05 (0.002)
S
W 1 C2
2XR
R1
0.25 (0.010)
GAGE PLANE
K C1 E Z VIEW AA
DIM A A1 B B1 C C1 C2 D E F G J K R1 S S1 U V V1 W Z 1 2 3
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CCCC EEEE CCCC EEEE
M
U
D T L-M
S
N
S
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Freescale Semiconductor, Inc.
MPC9449
NOTES
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MPC9449
NOTES
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Freescale Semiconductor, Inc.
MPC9449
Freescale Semiconductor, Inc...
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E Motorola, Inc. 2002.
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MPC9449/D
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